As a highly integrated semiconductor device requires a multi-layer metal wiring structure therein, a multi-layer metal wiring process having an etching process of the contact hole and the via hole, an anti-diffusion layer deposition process, a tungsten plug formation process, a chemical mechanical polishing process, a metal wiring deposition process and so on has been widely used.
After the etching process to form the contact hole and the via hole in such a metal wiring deposition process, formation of an oxide metal film layer, while the lower metal layer of the hole is exposed to the atmosphere, may yield higher resistance of the semiconductor. Further, the metal particle or the polymer including carbon may remain within the hole, and may occasionally block the hole.
In order to minimize an RC time constant delay time, a fluorinated silicate glass having a lower dielectric constant has been recently used instead of a conventional undoped silicate glass (USG) or tetra ethyl ortho silicate (TEOS) insulating film. However, such a fluorine component permeats into the anti-diffusion layer or an upper metal wiring layer, and may result in a cubical expansion, thus a detachment phenomenon of the metal wiring may occur.
Currently, an RF cleaning process has generally been used in order to solve the above problem.
However, such cleaning process also has an adverse effect in that the profile of the hole gets damaged during the RF cleaning process so that a bridge phenomenon in the contact hole or the via hole may occur. Further, the hole size miniaturizes so that the contact hole or the via hole may not completely be cleaned.